[玛丽]AMD推出Spartan UltraScale+芯片

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AMD 推出了适用于边缘应用的 Spartan UltraScale+ 可编程逻辑芯片。

这家总部位于加利福尼亚州圣克拉拉的公司表示，其最新的现场可编程门阵列（FPGA）是通过斥资 490 亿美元收购 Xilinx 获得的芯片系列，专为成本敏感的边缘应用而设计。

这些先进的 FPGA 具有高输入/输出 (I/O) 数量、功效和尖端安全功能，可满足嵌入式视觉、医疗保健、工业网络、机器人和视频应用等不同行业的需求。

“这是我们的第六代 Spartan FPGA 产品线。

这些是业界最普遍的 FPGA，在可编程逻辑领域众所周知，”AMD 产品营销高级经理 Rob Bauer 在新闻发布会上说道。

“重要的是要记住，从日常技术一直到一些突破性的进步，斯巴达确实为我们的世界赋予了力量。”

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Spartan UltraScale+ 器件代表了 FPGA 技术的重大飞跃，在基于 28 纳米 (nm) 芯片制造节点构建的 FPGA 中提供了业界最高的 I/O 与逻辑单元比率。

与上一代产品相比，它的总功耗降低了 30%，并且性能更加出色。

“For over 25 years, the Spartan FPGA family has played a vital role in powering achievements ranging from Mars rovers to life-saving automated defibrillators,” said Kirk Saban, corporate vice president in the Adaptive and Embedded Computing Group at AMD, in a statement. “The Spartan UltraScale+ family builds on proven 16nm technology, modernizing features, common design tools, and long product lifecycles to strengthen our market-leading FPGA portfolio and demonstrate our commitment to maximizing design longevity for customers.”

Flexible I/O and power efficiency

The Spartan UltraScale+ FPGAs are tailored for edge computing, offering high I/O counts and flexible interfaces that seamlessly integrate and interface with multiple devices or systems. With up to 572 I/Os and voltage support up to 3.3V, these FPGAs enable versatile connectivity for edge sensing and control applications. The family’s 16-nm fabric and support for various packaging sizes provide high I/O density in a compact footprint.

Spartan UltraScale+ FPGAs are estimated to reduce power consumption by up to 30% compared to the 28nm Artix 7 family. Leveraging 16nm FinFET technology and hardened connectivity, these FPGAs are equipped with a hardened LPDDR5 memory controller and PCIe Gen4 x8 support, ensuring both power efficiency and future-ready capabilities for users.

Security is a paramount concern in edge applications, and the Spartan UltraScale+ FPGAs address this by offering security features like Post-Quantum Cryptography with NIST-approved algorithms, ensuring IP protection against evolving cyber threats. A physical unclonable function provides each device with a unique fingerprint for enhanced security.

“Security is another aspect we want to touch on as we have more devices at the edge collecting more data,” Bauer said. “So the privacy of the user and protection of intellectual property is increasingly important. As we get more devices at the edge, the need for security is becoming a table stake for our customers.”

To prevent tampering, PPK/SPK key support helps manage obsolete or compromised security keys, while differential power analysis safeguards against side-channel attacks. The devices also incorporate a permanent tamper penalty to further protect against misuse. Enhanced single-event upset performance ensures fast and secure configuration with increased reliability.

The entire AMD FPGA portfolio, including the Spartan UltraScale+ family, is supported by the AMD Vivado Design Suite and Vitis Unified Software Platform. This allows hardware and software designers to leverage the productivity benefits of these tools and included IPs through a single designer cockpit from design to verification.

AMD Spartan UltraScale+ FPGA 系列预计于 2025 年上半年提供样品和评估套件，并立即提供文档。

预计 AMD Vivado 设计套件将于 2024 年第四季度开始提供工具支持。Spartan 芯片于 1998 年首次推出。

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